`timescale 1ns / 1ps
module SP(
    input clk,
    input data_in_en,
    input data_out_en,
    inout [15:0] data_bus,
    input rst_n,
    input SP_ADD_1,//SP<=SP+1控制信号
    input SP_SUB_1//SP<=SP-1控制信号
    );
    reg [7:0] data_reg;//8位寄存器SP
    always @(posedge clk ) begin
        if (rst_n == 1'b0) begin
            data_reg <= 8'h00;
        end
        else if (data_in_en) begin
            data_reg <= data_bus[7:0];
        end else if (SP_ADD_1) begin
            data_reg <= data_reg + 1;
        end else if (SP_SUB_1) begin
            data_reg <= data_reg - 1;
        end
    end
    assign data_bus = data_out_en ? {8'h00,data_reg} : 16'hzzzz;
    assign data_2_ALU = data_reg;


endmodule